1. Field of the Invention
The present invention relates to the field of integrated circuit fabrication; more specifically, it relates to a chemical-mechanical-polish method of fabricating integrated circuits.
2. Background of the Invention
Chemical mechanical processing for planarizing surfaces of semiconductor substrates is a technique that effects vertical dimensions of semiconductor structures. As integrated circuit devices become ever smaller in both the horizontal and vertical directions, control of vertical dimensions has become as important as control of horizontal dimensions in effecting yield and reliability. Therefore there is an ongoing need for chemical mechanical polishing processes with improved vertical dimension control.